1. Field of the Invention
The invention relates to an electrostatic discharge (ESD) clamp circuit, and more particularly to a high-voltage-tolerant ESD clamp circuit with low leakage current fabricated by low-voltage CMOS process.
2. Description of Related Art
General ESD clamp circuit is configured between the power terminal and the ground terminal of the electronic system. When the electronic system operates normally, the ideal ESD clamp circuit is required to be completely turned off without any leakage current. If the ESD pulse occurs, the ESD clamp circuit is required to be conductive to conduct the ESD pulse from the power terminal to the ground terminal to protect the electronic system.
In nanometer complementary metal oxide semiconductor (CMOS) process, the gate oxide is getting thinner with the evolution of the process technology, and the operation voltage is also decreasing. However, in an electronic system, there are usually several subsystems operating in different operation voltages. In order to make the integrated circuit be adapted to different operation voltages, in conventional method, high-voltage-tolerant subsystems are fabricated with the thicker gate oxide to prevent the gate oxide from electrical overstress (EOS). However, adding an additional mask during the fabricating process to fabricate the thick gate oxide increases the complexity of the process so that the yield decreases and the entire production cost increases.
To lower the production cost, the high-voltage-tolerant circuit fabricated by low-voltage CMOS process with the thin gate oxide is already a hot research topic, and so is the ESD clamp circuit.
FIG. 1 shows a circuit diagram of a conventional ESD clamp circuit. The ESD clamp circuit in FIG. 1 is fabricated by low-voltage CMOS process. If the low-voltage elements can only endure an operation voltage which is VDD, the circuit in FIG. 1 can endure an operation voltage which is two times of VDD. That is to say, the operation voltage Hi-Vcc provided by power terminal 210 is two times of VDD.
The ESD clamp circuit in FIG. 1 is divided into three parts: the discharge path 202, the control circuit 204, and the voltage divider including the p-channel metal oxide semiconductor field effect transistors (PMOS transistor) 302, 304. The PMOS transistors 302, 304 are diode-connected. Such voltage divider divides the operation voltage Hi-Vcc into two equal segments such that the voltage across the power terminal 210 and the node 303 equals to VDD and so does the voltage across the node 303 and the ground terminal. Therefore, each of the low-voltage elements in the circuit in FIG. 1 can operate normally without suffering from EOS.
The control circuit 204 turns off the PMOS transistors 206, 208 to cut off the discharge path 202. If the ESD pulse occurs at the power terminal 210, the control circuit 204 turns on the PMOS transistors 206, 208, thereby completing the discharge path 202 to conduct the ESD pulse to the ground terminal for protecting the electronic system.
FIG. 2 shows another circuit diagram of a conventional ESD clamp circuit. The ESD clamp circuits in FIGS. 1 and 2 work in the same way. The difference between them is that the control circuit 204 in FIG. 2 is simpler.
In the conventional process, there is less leakage current of the circuit elements. Referring to the circuits in FIGS. 1 and 2, the leakage current of the control circuits 204 and the discharge paths 202 is not obvious, so the voltage divider requires providing too much driving current. Therefore, the entire leakage current of the ESD clamp circuit is not severe.
However, in the nanometer advance process nowadays, due to the shrink of the size in the low-voltage elements, the leakage current of the control circuit 204 and the discharge path 202 increases tremendously, thereby the voltage divider has to provide large driving current to maintain the correct divided voltage, such as maintaining the voltage value of node 303 as VDD. Because the voltage divider requires providing large driving current and the voltage divider includes the low-voltage elements so that the leakage current of the voltage divider is more severe and consumes most of the leakage current of the entire ESD clamp circuit; in addition, the layout area occupied by the voltage divider cannot be reduced. Due to the leakage current, the ESD clamp circuits used in advance process as shown in FIGS. 1 and 2 do not meet the consideration principle of saving the energy and lowering the cost.
FIG. 3 shows another circuit diagram of a conventional ESD clamp circuit. The ESD clamp circuit in FIG. 3 is fabricated by low-voltage CMOS process as well. If the low-voltage elements can only endure an operation voltage which is VDD, the circuit in FIG. 3 can endure an operation voltage which is three times of VDD.
The ESD clamp circuit in FIG. 3 works in the same way as those in FIGS. 1 and 2. The ESD clamp circuit in FIG. 3 includes the discharge path 110, the control circuit 120, and the voltage divider 130, wherein the discharge path 110 includes the silicon-controlled rectifier (SCR) 115. Six diode-connected PMOS transistors Md1-Md6 in series are used in the voltage divider 130 to divide the operation voltage which is three times of VDD by three to prevent each of the low-voltage elements of the circuit in FIG. 3 from EOS. When the ESD pulse occurs, the control circuit 120 outputs trigger current I_trig, completing the discharge path 110 to conduct the ESD pulse to the ground terminal.
Because the operation principle is the same as those in FIGS. 1 and 2, the ESD clamp circuit in FIG. 3 has the same problem of severe leakage current in the advance process.